1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to the cell array structure of an MRAM (Magnetoresistive Random Access Memory).
2. Description of the Related Art
An MRAM is a device which performs memory operations by storing “1”- or “0”-information using the magnetoresistive effect, and is expected as a rewritable memory device which exhibits nonvolatility, high integration, high reliability, and high-speed operation as compared with conventional DRAMs, EEPROMs, and the like.
As an MRAM cell, the use of a GRM (Giant MagnetoResistive) element using a multilayer metal magnetic film/insulating film and a change in magnetoresistance due to a spin-polarized tunnel effect or a TMR (Tunneling MagnetoResistive) element has been proposed. A TMR element has an insulating film sandwiched between two magnetic films. This structure can create two states, i.e., a state where the directions of the spins of the two magnetic films are parallel to each other, and a state where the directions of the spins are antiparallel to each other. When the directions of spins become parallel to each other, the tunnel current flowing through the thin insulating film interposed between the two magnetic films increases, and the resistance value of the TMR element decreases. In contrast to this, if the directions of spins become antiparallel to each other, the tunnel current decreases, and the resistance value of the TMR element increases. “0”-data and “1”-data can be discriminated from each other in accordance with the magnitude of this resistance value.
The structure of an MRAM using the above TMR element as a memory cell is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2000-163950. FIG. 1A shows the arrangement of the MRAM disclosed in this reference.
As shown in FIG. 1A, in the MRAM cell array, (m×4) MRAM cells MC11 to MCm4 are arranged in the form of a matrix at the intersections of a plurality of word lines WL1 to WLm (m: integer) and sense lines SL1 to SL4 perpendicular to the word lines WL1 to WLm. One of the magnetic films of each of the MRAM cells MC11 to MCm4 is connected to one of the word lines WL1 to WLm, and the other magnetic film is connected to one of the sense lines SL1 to SL4. One end of each of the sense lines SL1 to SL4 is connected to ground potential via a corresponding one of ground switches S401 to S404, the other end of each sense line is connected to a corresponding one of read/write sections 100-1 to 100-4.
Each of the read/write sections 100-1 to 100-4 includes a write switch S500, read switch S600, write current source 110, and sense circuit 120. The write current source 110 and sense circuit 120 are connected to the respective sense lines SL1 to SL4 via the write switch S500 and read switch S600. The sense circuit 120 has an operational amplifier 130 and a current/voltage converter (resistive element) 140. The operational amplifier 130 has a noninverting input terminal connected to ground potential, an inverting input terminal connected to one of the sense lines SL1 to SL4 via the read switch S600, and an output terminal. The resistive element 140 has one end connected to the inverting input terminal of the operational amplifier 130 and the other end connected to the output terminal of the operational amplifier 130.
The read operation of the MRAM having the above arrangement will be described next by exemplifying a case where data is read out from the MRAM cell MC14. First of all, a voltage Vread is applied to the word line WL1 to which the selected cell MC14 is connected. In addition, the ground switch S404 connected to the sense line SL4 to which the selected cell MC14 is connected is turned off, and the remaining ground switches S401 to S403 are turned on. Furthermore, the write switch S500 in the read/write section 100-4 is turned off, and the read switch S600 is turned on. The voltage Vread is then applied to the word line WL1. As a result, a read current Iread flows through the selected cell MC14. This read current Iread flows into the operational amplifier 130 via the sense line SL4 and read switch S600. The current Iread is converted into a voltage by the resistive element 140. This voltage is then output as a read voltage Vout from the output terminal of the operational amplifier 130.
According to the above read method, the read precision can be improved by eliminating the influence of parasitic impedance existing in the selected sense line SL4. This point will be described with reference to FIG. 1B. FIG. 1B is a circuit diagram showing a parasitic impedance network existing in the selected sense line SL4 in reading data from the MRAM cell MC14.
As shown in FIG. 1B, when data is read out from the selected cell MC14, parasitic impedance networks 150 and 160-1 to 160-m exist in parallel with the selected cell MC14. The parasitic impedance network 150 is a parallel circuit of the memory cell impedances of the MRAM cells MC11 to MC13 connected to the selected word line WL1. In addition, the parasitic impedance networks 160-1 to 160-n (n=m−1) are connected in series with the parallel circuit of the memory cell impedances of the MRAM cells MC24 to MCm4 connected to the selected sense line SL4 and the memory cell impedances of the MRAM cells MC21 to MC23, MC31 to MC33, MC41 to MC43, . . . , MCm2 to MCm3 connected to the unselected word lines WL2 to WLm to which the respective MRAM cells MC24 to MCm4 are connected.
According to the above read method, the selected sense line SL4 is connected to the inverting input terminal of the operational amplifier. Therefore, the selected sense line SL4 is virtually grounded. In addition, all the unselected sense lines SL1 to SL3 are grounded. Therefore, the influences of parasitic impedances produced by unselected cells can be eliminated, and the information written in the selected cell can be accurately read out.
According to the conventional MRAM, however, as the number of memory cells connected in parallel with each other increases, currents flowing to parasitic impedances increase in the early stage of sense operation, resulting in an increase in current consumption. As the currents flowing to the parasitic impedances increase, the amount of current flowing into the operational amplifier decreases. That is, a read signal decreases. As a consequence, it takes a longer period of time to stabilize the output of the operational amplifier by virtually grounding a bit line after the operational amplifier is started. Consequently, the data read rate decreases, and the data read precision deteriorates. This may make it difficult to increase the number of memory cells, i.e., the integration degree of an MRAM.